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MPEG2 1chip Audio/Video Encoder MB86391 Product Specification
Revision 1.1 12, November 2001
Copyright (c) FUJITSU LIMITED ALL RIGHTS RESERVED
MB86391 Product Specification Rev. 1.1
12, November 2001
FUJITSU LIMITED Proprietary and Confidential
u u u u u
Information contained in this specification is subject to change without notice for improvement. No part of this specification may be reproduced or transmitted in any form or by any means for any purpose without the express written permission of Fujitsu Ltd. The furnishing of this specification does not give users any license to Fujitsu's industrial property rights. Fujitsu is not liable for infringement of third party patent rights, industrial property rights, or other rights that might result from the use of contents provided in this specification. Use of product in any manner that complies with the MPEG-2 standard is expressly prohibited without a license under applicable patents in the MPEG-2 patent portfolio, which license is available from MPEG LA, L.L.C., 250 steele street, suite 300, Denver, Colorado, USA 80206
MB86391 Product Specification Rev. 1.1
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Contents 1 Overview ......................................................................................................................................... 1 1.1 Product Overview ...................................................................................................................... 1 1.2 System Configuration................................................................................................................. 2 1.3 Specification Overview ............................................................................................................... 3 1.3.1 1.3.2 1.3.3 Major Items................................................................................................................... 3 Function List ................................................................................................................. 3 Package....................................................................................................................... 4
1.4 Block Diagram .......................................................................................................................... 5 2 Pin Description................................................................................................................................. 6 2.1 I/O Signals ............................................................................................................................... 6 2.2 Pin Arrangement ....................................................................................................................... 7 2.2.1 2.2.2 Pin Arrangement Diagram............................................................................................... 7 Pin Numbers ................................................................................................................. 8
2.3 Pin Functions............................................................................................................................ 9 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.3.7 2.3.8 3 Overall Control .............................................................................................................. 9 Host/SDRAM interface.................................................................................................. 10 Serial Interface...........................................................................................................111 SDRAM Interface for Video Encoding............................................................................122 Video Input Interface...................................................................................................133 Audio Input Interface...................................................................................................144 Bit Stream Output Port.................................................................................................155 Test Signals...............................................................................................................166
Functional Description....................................................................................................................177 3.1 Host/SDRAM Interface............................................................................................................177 3.1.1 Access by External Master...........................................................................................188 3.1.1.1 MB86391 Internal Resource Accessing..............................................................188 3.1.1.2 SDRAM Accessing........................................................................................... 20 3.1.1.3 External Resource Accessing...........................................................................244 3.1.2 Internal Controller Master Accessing .............................................................................266 3.1.2.1 External Resource Accessing...........................................................................266 3.1.2.2 External Boot ROM Read.................................................................................288 3.1.3 Interruption ................................................................................................................299 3.1.3.1 Internal Controller Interrupt Input (IRQ9:8)..........................................................299 3.1.3.2 Host Interrupt Output (XEXTIRPT) ....................................................................299 3.1.4 Address Map............................................................................................................... 30
3.2 Serial Interface.......................................................................................................................311
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3.2.1 3.2.2
Serial Interface Receive Operations ..............................................................................311 Serial Interface Send Operations ..................................................................................322
3.3 SDRAM Interface for Video Encoding........................................................................................333 3.4 Video Input Interface...............................................................................................................344 3.4.1 Input Formats.............................................................................................................355
3.5 Audio Input Interface...............................................................................................................366 3.5.1 3.5.2 Master/Slave Mode...................................................................................................... 37 Input Formats.............................................................................................................377
3.6 Bit Stream Output Port ............................................................................................................388 3.7 Error Notification Function .......................................................................................................411 3.8 Boot Operations.....................................................................................................................422 3.8.1 3.8.2 3.8.3 4 Downloading from the External ROM.............................................................................433 Serial Download .......................................................................................................... 43 Direct SDRAM Downloading.........................................................................................433
Electrical Characteristics (Provisional Target Specifications)................................................................444 4.1 Maximum Ratings...................................................................................................................444 4.2 Recommended Operating Conditions ......................................................................................... 45 4.2.1 4.2.2 Recommended Operating Conditions ............................................................................. 45 Precautions When Connecting the Power ....................................................................... 45
4.3 DC Characteristics .................................................................................................................. 46 4.4 AC Characteristics................................................................................................................... 47 4.4.1 Overall Control ............................................................................................................ 47 4.4.1.1 Clock Input...................................................................................................... 47 4.4.1.2 Reset Input ..................................................................................................... 48 4.4.2 Host/SDRAM Interface................................................................................................. 49 4.4.2.1 Host Interface.................................................................................................. 49 4.4.2.2 SDRAM Interface Signals ................................................................................. 52 4.4.3 4.4.4 4.4.5 4.4.6 4.4.7 Serial Interface............................................................................................................ 54 SDRAM Interface for Video Encoding............................................................................. 56 Video Input Interface.................................................................................................... 58 Audio Input Interface.................................................................................................... 59 Bit Stream Output Port.................................................................................................. 63
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1 Overview
1.1 Product Overview
The MB86391 (MPEG2 1chip Audio/Video Encoder) is an LSI that accomplishes all of video encoding, audio encoding, and video and audio encode stream data multiplexing with a single chip rather than several LSIs as in the past. This LSI enables you to minimize the size, cost and power consumption of MPEG2 application systems, such as digital video recorders. An easy control command interface is achieved by firmware dedicated to the internal controller.
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1.2
System Configuration
Fig. 1.2 shows an example system configuration using the MB86391.
Serial interface XMBREQ, XBREQ
System Controller
Bus Switch
XBGRNT D31:0, ADRS27 :26, 17:2, control XBUSEN, BUSDIR, XBGRNT External boot ROM MPEG2 Decoder SDRAM control
Bit stream output port
MB86391
16Mbit SDRAM (x16bit) 64Mbit SDRAM (x32bit)
or
Video encoding SDRAM
D/A
16Mbit SDRAM ( x16bit) or
64Mbit SDRAM (x32bit)
Audio I/F
Video I/F
Video output
Audio output
Record/ com mu nication I/O Controller/TBC SDRAM
Audio input
Video input
Fig. 1.2 : System configuration (Example))
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1.3
Specification Overview
1.3.1 Major Items
Table 1.3.1 : Major items
Model Function Operating frequency Technology Supply voltage Power consumption Operating temperature Package
MB86391 MPEG2 1chip Audio/Video encoder 54MHz (27MHz for some) [27MHz input clock frequency, 54MHz clock generated by internal PLL] 0.18m, Al 4 layers I/O 3.0 to 3.6V, Internal 1.65 to 1.95V T.B.D Ta = -20 to 85C
208pin HQFP(FPT-208P-M04)
1.3.2 Function List
Table 1.3.2 : Function list Encoding Compliant to ISO/IEC13818-2 (MPEG2 video)MP@ML and ISO/IEC11172-2 (MPEG1 video) When interlacing at 29.97Hz Compatible with size 32mx32n less than 720x480 (m, n : any integers) When interlacing at 25Hz : Compatible with size 32mx32n less than 720x576 (m, n : any integers) D1 8bit parallel, YC multiplex 8bit parallel Max. 15Mbps ISO/IEC11172-3 (MPEG1 audio) layer 1/2-compliant 32kHz, 44.1kHz, 48kHz 2 (mono, stereo, dual, joint stereo) LR multiplex serial
Video encoder
Screen size
Video input interface Bit rate Encoding method Sampling frequency Audio encoder Channel count Audio input interface Bit rate
Max. 448kbps ISO/IEC11172-1 (MPEG1 system) Encoding method ISO/IEC13818-1 (MPEG2 system PS/TS) Multiplexer [Can also output to mono media in ES and PES formats.] Stream output 8bit parallel Bit rate Max. 20Mbps (CBR/VBR) Overall controller Internal 32bit RISC processor External SDRAM I/F for Connects two 16Mbit (1Mx16bits) or one 64Mbit (2Mx32bits) memory video encoding interface Host/SDRAM I/F Connects two 16Mbit (1Mx16bits) or one 64Mbit (2Mx32bits) Serial interface One internal port for overall controller BOOT and command I/F Absorbs timing errors due to disarrayed input video images by Time base corrector temporarily buffering before reading video input data on an SDRAM connected to the host/SDRAM I/F.
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1.3.3 Package
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1.4
Block Diagram
Fig. 1.4 shows a block outline diagram of this LSI and Table 1.4 lists the functional overviews of major blocks.
Serial interface
Host/SDRAM interface
Host/SDRAM interface controller
Serial interface controller Boot ROM
Controller (32bit RISC processor)
Video encoder Video input interface TBC controller Multiplexer Video encoding SDRAM interface Audio encoder Audio input interface SRAM (8kx8) 27MHz Clock input (27MHz) PLL 54MHz Bit stream output port
MB86391
Fig. 1.4 : MB86391 block diagram Table 1.4 : Overview of major block functions Block name
Video encoder Audio encoder Multiplexer Controller TBC controller
Functional overview
Encodes video data input from the TBC controller to create video streams. Encodes audio data input from outside to create audio streams. Multiplexes video and audio streams generated by video and audio encoders to generate 8bit parallel stream data for output to outside. Controls the entire MB86391 using dedicated firmware. Stores video data input from outside in an external SDRAM and then input it to the video encoder. The TBC (Time Base Corrector) function is accomplished by buffering video data in the SDRAM. Arbitrates SDRAM and MB86391 internal register access requests from MB86391 internal blocks and external master devices. Also used as the command interface with the host. Downloads dedicated firmware to the external SDRAM via this interface at the time of serial booting. Also used as a command interface with the host. Converts the format of video streams the video encoder has generated and outputs to the multiplexer. Controls DMA transfer among MB86391 blocks and external SDRAMs. Stores the boot program for the internal controller.
Host/SDRAM interface controller
Serial interface controller Video PES converter DMA controller Boot ROM
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2 Pin Description
2.1 I/O Signals
Fig. 2.1 shows the I/O signals of this LSI.
12
CLKSEL Overall control signals (4 in total) MCLKI XRESET PLLTHR BCLK
2 32
SDADRS11:0 SDDATA31:0 SDDQM XSDWE XSDCAS XSDRAS XSDCS SDCKE SDCLK VCLK XVSYNC XHSYNC
2
Video encoding SDRAM interfaces (51 in total)
ADRS27:26
16
ADRS17:2
32
D31:0 IRQ9:8 XAS XRDWR XCS0 XCS5:4 XBMREQ Host/SDRAM interfaces (71 in total) XBREQ XBGRNT XBUSEN BUSDIR XREADY XEXTIRPT XERROR XSPWE XSPCAS XSPRAS SPCKE SPSDCLK SCLK Serial interfaces (3 in total) SDATAIN SDATAOUT
47 8 2
FIELD XVALID
Video input interfaces (13 in total)
MB86391
8
DVIDEO7:0 ASCLK ALRCK ACLK ADATA STCLK STREQ STEN STDATA7:0 TSPSSYNC
Power/GND
3
Audio input interfaces (4 in total)
Bit stream output ports (12 in total)
(47 in total) (3 in total)
Test signals
Total external pin count :208
Fig. 2.1 : I/O signal diagram
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2.2
Pin Arrangement
2.2.1 Pin Arrangement Diagram
SDDATA26 SDDATA25 SDDATA24 SDDATA0 SDDATA1 SDDATA2 VDDI SDDATA3 SDDATA4 SDDATA5 SDDATA6 SDDATA7 SDDATA15 SDDATA14 VDDE VSS SDDATA13 SDDATA12 SDDATA11 SDDATA10 SDDATA9 SDDATA8 VSS VDDE VCLK XHSYNC XVSYNC FIELD XVALID VDDI DVIDEO7 DVIDEO6 DVIDEO5 DVIDEO4 DVIDEO3 DVIDEO2 DVIDEO1 DVIDEO0 VDDE VSS ADRS14 ADRS13 ADRS12 ADRS2 ADRS3 ADRS4 VSS VDDE VDDI ADRS11 ADRS10 ADRS9
VDDE VSS SDDATA27 SDDATA28 SDDATA29 SDDATA30 SDDATA31 SDDATA23 SDDATA22 VDDI SDDATA21 SDDATA20 SDDATA19 SDDATA18 SDDATA17 SDDATA16 VSS VDDE SDDQM XSDWE XSDCAS XSDRAS XSDCS SDCKE SDCLK VDDI SDADRS3 SDADRS4 SDADRS5 SDADRS6 SDADRS7 SDADRS8 VDDE VSS SDADRS9 SDADRS2 SDADRS1 SDADRS0 SDADRS10 SDADRS11 VSS VDDE ASCLK ADATA VPDX TESTMODE ALRCK ACLK STREQ XTST VDDE VSS
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
MB86391 HQFP208(FPT-208P-M04)
INDEX
ADRS8 ADRS7 ADRS6 ADRS5 VDDE VSS SPCKE SPSDCLK VDDI XSPWE XSPCAS XSPRAS ADRS15 ADRS16 ADRS17 ADRS26 ADRS27 VSS VDDE D0 D1 D2 VDDI D3 D4 D5 VDDE VSS D6 D7 D15 D14 D13 D12 D11 D10 D9 D8 VDDI D16 D17 D18 VSS VDDE D19 D20 D21 D22 D23 D31 D30 D29
MB86391 Product Specification Rev. 1.1
VDDI TSPSSYNC STEN STDATA7 STDATA6 STDATA5 STDATA4 AVDD AVSS STDATA3 STDATA2 STDATA1 STDATA0 VSS VDDE STCLK SDATAOUT SDATAIN SCLK VDDI XREADY XRDWR XAS AVSS AVDD MCLKI PLLTHR CLKSEL XBREQ XBMREQ IRQ8 IRQ9 XRESET VDDE VSS XBGRNT BUSDIR XBUSEN XEXTIRPT XERROR XCS0 XCS4 XCS5 BCLK VSS VDDE D24 D25 VDDI D26 D27 D28
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Fig. 2.2.1 : Pin arrangement diagram
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2.2.2 Pin Numbers
Table 2.2.2 : Pin number list
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 I/O - O O O O O O - - O O O O - - I O I I - I/O I/O I/O - - I I I I I I I I - - O O O O O O O O O - - I/O I/O - I/O I/O I/O Pin name VDDI TSPSSYNC STEN STDATA7 STDATA6 STDATA5 STDATA4 AVDD AVSS STDATA3 STDATA2 STDATA1 STDATA0 VSS VDDE STCLK SDATAOUT SDATAIN SCLK VDDI XREADY XRDWR XAS AVSS AVDD MCLKI PLLTHR CLKSEL XBREQ XBMREQ IRQ8 IRQ9 XRESET VDDE VSS XBGRNT BUSDIR XBUSEN XEXTIRPT XERROR XCS0 XCS4 XCS5 BCLK VSS VDDE D24 D25 VDDI D26 D27 D28 Pin No. 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 I/O I/O I/O I/O I/O I/O I/O I/O I/O - - I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - - I/O I/O I/O - I/O I/O I/O - - I/O I/O I/O I/O I/O O O O - O O - - I/O I/O I/O I/O Pin name D29 D30 D31 D23 D22 D21 D20 D19 VDDE VSS D18 D17 D16 VDDI D8 D9 D10 D11 D12 D13 D14 D15 D7 D6 VSS VDDE D5 D4 D3 VDDI D2 D1 D0 VDDE VSS ADRS27 ADRS26 ADRS17 ADRS16 ADRS15 XSPRAS XSPCAS XSPWE VDDI SPSDCLK SPCKE VSS VDDE ADRS5 ADRS6 ADRS7 ADRS8 Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 I/O I/O I/O I/O - - - I/O I/O I/O I/O I/O I/O - - I I I I I I I I - I I I I I - - I/O I/O I/O I/O I/O I/O - - I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O Pin name ADRS9 ADRS10 ADRS11 VDDI VDDE VSS ADRS4 ADRS3 ADRS2 ADRS12 ADRS13 ADRS14 VSS VDDE DVIDEO0 DVIDEO1 DVIDEO2 DVIDEO3 DVIDEO4 DVIDEO5 DVIDEO6 DVIDEO7 VDDI XVALID FIELD XVSYNC XHSYNC VCLK VDDE VSS SDDATA8 SDDATA9 SDDATA10 SDDATA11 SDDATA12 SDDATA13 VSS VDDE SDDATA14 SDDATA15 SDDATA7 SDDATA6 SDDATA5 SDDATA4 SDDATA3 VDDI SDDATA2 SDDATA1 SDDATA0 SDDATA24 SDDATA25 SDDATA26 Pin No. 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 I/O - - I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O - - O O O O O O O - O O O O O O - - O O O O O O - - I I I I I/O I/O I I - - Pin name VDDE VSS SDDATA27 SDDATA28 SDDATA29 SDDATA30 SDDATA31 SDDATA23 SDDATA22 VDDI SDDATA21 SDDATA20 SDDATA19 SDDATA18 SDDATA17 SDDATA16 VSS VDDE SDDQM XSDWE XSDCAS XSDRAS XSDCS SDCKE SDCLK VDDI SDADRS3 SDADRS4 SDADRS5 SDADRS6 SDADRS7 SDADRS8 VDDE VSS SDADRS9 SDADRS2 SDADRS1 SDADRS0 SDADRS10 SDADRS11 VSS VDDE ASCLK ADATA VPDX TESTMODE ALRCK ACLK STREQ XTST VDDE VSS
VDDE : 3.3V power supply, VDDI : 1.8V power supply, AVDD : 1.8V power supply to PLL VSS, AVSS : ground
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2.3
Pin Functions
2.3.1 Overall Control
Table 2.3.1 : Overall control pins
Pull up /down
The pin functions of this LSI are shown below.
Pin No.
Pin symbol
Pin name
Bit I/O Active
Description Internal controller operating frequency selection input pin. When the screen size is D1, select 54MHz operations. `H' = 54MHz operations `L' = 27MHz operations Operating clock (27MHz) input pin Reset signal input pin Internal PLL control signal input pin (See figure on page 52)
28
CLKSEL
Internal Clock Select Main Clock Input Reset PLL through
1
I
-
-
26 33 27
MCLKI XRESET PLLTHR
1 1 1
I I I
- L -
- - -
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2.3.2 Host/SDRAM interface
Table 2.3.2 : Host/SDRAM interface pins
Pin No. 44 88,89 Pin symbol BCLK ADRS27:26 Pin name Bus Clock Address 27:26 Address 17:2 Bit I/O Active 1 2 O I/O - - - Pull up/down - - - 32bit data I/O pins Data31:0 32 I/O - - Pin function Host/SDRAM interface bus clock (27MHz) output pin Address (upper 2bits) I/O pins Address (lower 16bits) I/O pins 16 I/O
90 to 92, 116 to 114, ADRS17:2 107 to 101, 111 to 113 55 to 50,48,47, 56 to 60, 63 to 65, D31:0 74 to 67,75,76, 79 to 81, 83 to 85 32,31 23 22 41 43,42 30 29 36 38 37 21 39 40 95 94 IRQ9:8 XAS XRDWR XCS0 XCS5:4 XBMREQ XBREQ XBGRNT XBUSEN BUSDIR XREADY XEXTIRPT XERROR XSPWE XSPCAS
Interrupt Request 9:8 Address Strobe Read/Write Chip Select 0 Chip Select 5:4 Burst Mode Request Bus Request Bus Grant Bus Buffer Enable Bus Buffer Direction Ready External Interrupt Error Write Enable Column Address Strobe Row Address Strobe Clock Enable SDRAM Clock
2 1 1 1 2 1 1 1 1 1 1 1 1 1 1
I I/O I/O O O I I O O O I/O O O O O
L L - L L L L L L - L L L L L
pullup - - pullup - pullup pullup - - - - - - - - - - -
Interrupt request input pins. When not in use, connect to either OPEN or VDDE. Address strobe I/O pin Read/write I/O pin: `H' = Read `L' = Write Chip select 0 output pin Chip select 5:4 output pins Burst transfer request input pin Bus privilege request input pin Bus grant output pin Bus buffer enable output pin Bus buffer direction control output pin Ready I/O pin External host interruption request pin Error output pin Write enable output pin to SDRAM connected to host/SDRAM interface Column address strobe output pin to SDRAM connected to host/SDRAM interface Row address strobe output pin to SDRAM connected to host/SDRAM interface Clock enable output pin to SDRAM connected to host/SDRAM interface Clock output pin to SDRAM connected to hos t/SDRAM interface
93 98 97
XSPRAS SPCKE SPSDCLK
1 1 1
O O O
L H -
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2.3.3 Serial Interface
Table 2.3.3: Serial interface pins
Pin No. 19 18 17 Pin symbol SCLK SDATAIN SDATAOUT Pin name Serial Clock Serial Data Input Serial Data Output Bit I/O Active 1 1 1 I I O - - - Pull up/down - - - Pin function Serial I/F serial clock input pin. Serial I/F data input pin. Serial I/F data output pin.
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2.3.4 SDRAM Interface for Video Encoding
Table 2.3.4: SDRAM interface pins for video encoding
Pin No. 196,195,191, 188 to 183, 192 to 194 163 to 159, 156 to 154, 164,165, 167 to 172, 144,143, 140 to 135, 145 to 149, 151 to 153 175 Pin symbol SDADRS11:0 Pin name SDRAM Address Bit I/O 12 O Active - Pull up/down - Pin function Address output (12bits) pins to SDRAM connected to the video encoding SDRAM interface Data I/O (32bits) pins to SDRAM connected to the video encoding SDRAM interface pullup
SDDATA31:0
SDRAM Data
32 I/O
-
SDDQM
Input Mask /Output Enable Write Enable Column Address Strobe Row Address Strobe Chip Select Clock Enable SDRAM Clock
1
O
H
- - - - - - -
176
XSDWE
1
O
L
177
XSDCAS
1
O
L
178
XSDRAS
1
O
L
179
XSDCS
1
O
L
180 181
SDCKE SDCLK
1 1
O O
H -
Data mask output pin to SDRAM connected to the video encoding SDRAM interface Write enable output pin to SDRAM connected to the video encoding SDRAM interface Column address strobe output pin to SDRAM connected to the video encoding SDRAM interface Row address strobe output pin to SDRAM connected to the video encoding SDRAM interface Chip select output pin to SDRAM connected to the video encoding SDRAM interface Clock enable output pin to SDRAM connected to the video encoding SDRAM interface Clock output pin to SDRAM connected to the video encoding SDRAM interface
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2.3.5 Video Input Interface
Table 2.3.5: Video input interface pins
Pin No. 132 130 131 129 128 126 to 119 Pin symbol VCLK XVSYNC XHSYNC FIELD XVALID DVIDEO7:0 Pin name Video Clock Vertical Sync Horizontal Sync Field Data Valid Digital Video Bit I/O Active 1 1 1 1 1 8 I I I I I I - L L - L - Pull up/down - - - - - - Pin function Video clock input pin. Vertical sync input pin. Horizontal sync input pin. Field ID input pin. Input pin to indicate that valid data exists at DVIDEO7:0. Video input data input pin.
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2.3.6 Audio Input Interface
Table 2.3.6:Audio input interface pins
Pin No. Pin symbol Pin name Audio System Clock Audio L/R Clock Audio Bit Clock Audio Serial Data Bit I/O Active Pull up/down - - - - Pin function System clock input pin for audio. Input clock 256 times the audio sampling frequency. Must be in sync with MCLKI. Audio sampling clock pin. The pin outputs in master mode and inputs in slave mode. Audio bit clock pin. The pin outputs in master mode and inputs in slave mode. Audio serial data input pin.
199
ASCLK
1
I
- - - -
203 204 200
ALRCK ACLK ADATA
1 1 1
I/O I/O I
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2.3.7 Bit Stream Output Port
Table 2.3.7: Bit stream output port pins
Pin No. Pin symbol Pin name Bit Stream Transfer Clock Bit Stream Transfer Request Bit Stream Output Enable Bit Stream Data7:0 Bit I/O Active Pull up/down pullup Pin function Bit stream transfer clock input pin. The clock is for stream reading in transfer clock sync mode. Bit stream transfer request input pin. When transferring streams in transfer clock sync mode, connect to VDDE. Bit stream output enable output pin.
16
STCLK
1
I
-
205
STREQ
1
I
H
-
3
STEN
1
O
H
- - Bit stream output port (8bit) pin. The error code is output in case of an error. This output pin indicates the leading data of the TS/PS packet. 1cycle is set to 'H" at the sync byte of the packet in the case of TS and at the leading byte of the PACK header or PS end code in the case of PS.
4 to 7,10 to 13
STDATA7:0
8
O
-
2
TSPSSYNC
TS/PS Sync
1
O
H
-
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2.3.8 Test Signals
Table 2.3.8: Test pins
Pin No. 201 202 206 Pin symbol VPDX TESTMODE XTST Pin name - - - Bit I/O Active 1 1 1 I I I H H L Pull up/down - Pin function
A test pin. For typical usage, connect to VSS. A test pin. For typical usage, connect to pull down OPEN or VSS. pull up A test pin. For typical usage, connect to OPEN or VDDE.
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3 Functional Description
3.1 Host/SDRAM Interface
The host/SDRAM interface arbitrates bus privilege between the external master connected to this interface and MB86391 internal resources and also controls access to external resources (such as SDRAM, boot ROM, and MPEG decoder). Fig. 3.1 shows an example host/SDRAM interface connection. The next and subsequent chapters show timing diagrams for various accesses.
BCLK(O)[27MHz] XAS(I/O) XRDWR(I/O) XREADY(I/O) XCS5,4,0(O) XCS4 or 5 XCS0 XBREQ(I) External master B A DIR OE
Bus transceiver (equivalent to LVx245)
XBMREQ(I) XBGRNT(O) ADRS27:26,17:2(I/O)
B
A DIR OE
D31:0( I/O) BUSDIR(O) XBUSEN(O)
CS OE MPEG decoder Boot ROM D A15:0 A18:16 SDRAM
16Mbitx2 (x16bit type) or 64Mbitx1 (x32bit type)
SPSDCLK(O)[54MHz] XSPRAS(O) XSPCAS(O) XSPWE(O)
XCS, DQM
Fixed to "L" STDATA2:0(O)
MB86391
Fig. 3.1: Host/SDRAM interface connection (Example) Note: In the case of a 16Mbit SDRAM, connect ADRS13:2 to BA, A10:0. In the case of a 64Mbit SDRAM, connect ADRS13:2 to BA1, A10:0. Keep BA0 fixed to 'H' or 'L.' Install the MB86391 and the SDRAM as physically close as possible. Pull up the SPSDCLK signal line with a resistance of 200 in the vicinity of the SDRAM. The SPSDCLK signal line must be in a pattern of a single stroke, from the MB86391, the sending end, through the SDRAM CLK to the point of connection to the pull-up resistance. Other signal lines do not require any particular handling such as pull-up. However, take care to avoid unnecessary routing when designing patterns. MB86391 can connect each bit width of boot ROM such as x8bit, x16bit and x32bit. (Recommended x16bit) Recommended boot ROM size is over 4Mbit. Fig. 3.1: Host/SDRAM interface connection (Example)
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3.1.1 Access by External Master
Shown below are diagrams of timing according to which the external master accesses MB86391 internal resources and SDRAM and peripheral chips (MPEG2 decoder LSI, for example) connected to this interface.
3.1.1.1 MB86391 Internal Resource Accessing
(a) Write
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS( I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4,0(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' All ` H' All `H ' All ` H'
Fig. 3.1.1.1a:MB86391 internal resource access timing (Write) (1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26, 17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction) and asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to Hi-Z. (5) After writing data, the MB86391 asserts XREADY and notifies the external master of write completion. (6) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state. Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed.
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(b) Read
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS( I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4,0(O) XREADY(I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' All `H ' All `H ' All ` H'
Fig. 3.1.1.1b: MB86391 internal resource access timing (Read)) (1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26, 17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XRDWR and ADRS27:26, 17:2 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to Hi-Z. (5) The MB86391 sets BUSDIR to 'H' (read direction) to allow read data output. (6) The MB86391 outputs valid data to D31:0 at the same time as it asserts XREADY (the external master fetches read data at this timing). (7) The MB86391 negates XBUSEN and resets to its normal state. Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed.
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3.1.1.2 SDRAM Accessing
(a) Single write
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS( I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4,0(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' All ` H' All `H '
All `H'
RA
CA
All `H '
Fig. 3.1.1.2a:SDRAM access timing (Single write)
(1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2, and D31:0 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to Hi-Z. (5) The MB86391 re-outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 asserts the XREADY signal during the cycle to write data to the SDRAM and notifies it to the external master. (7) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state. Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed.
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(b) Single read
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS( I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4,0(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' All ` H' All `H '
All ` ' H
RA
CA
All `H '
Fig. 3.1.1.2b: SDRAM access timing (Single read) (1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XRDWR and ADRS27:26, 17:2 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26, 17:2 to Hi-Z. (5) The MB86391 re-outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 sets BUSDIR to 'H' (read direction) to allow read data output. (7) The MB86391 asserts the XREADY signal during the SDRAM data read cycle and notifies it to the external master. (8) The MB86391 negates XBUSEN and resets to its normal state. Note: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed.
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(c) Burst write
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS( I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4,0(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' WD WD+1 WD+2 WD+3 All ` H' All `H '
All ` ' H
RA
CA
CA+1
CA+2
CA+3
All `H '
Fig. 3.1.1.2c: SDRAM access timing (Burst write)) (1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XBMREQ, XRDWR, ADRS27:26, 17:2, and D31:0 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to Hi-Z. (5) The MB86391 re-outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 asserts the XREADY signal during the cycle to write data to the SDRAM and notifies it to the external master. (7) The MB86391 negates XBUSEN, sets BUSDIR to 'H' (read direction), and resets to normal state. Notes: The burst length is fixed to 4. After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed. Burst access extending over 1 KB is not allowed.
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(d) Burst read
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS(I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4,0(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' WD WD+1 WD+2 WD+3 All ` H' All `H '
All `H '
RA
CA
CA+1
CA+2
CA+3
All `H '
Fig. 3.1.1.2d: SDRAM access timing (Burst read) (1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction and then asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XBMREQ, XRDWR and ADRS27:26, 17:2 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26,17:2 to Hi-Z. (5) The MB86391 re-outputs the address fetched in (4) to the SDRAM at the command. (6) The MB86391 sets BUSDIR to 'H' (read direction) to allow SDRAM read data output. (7) The MB86391 asserts the XREADY signal during the SDRAM data read cycle and notifies it to the external master. (8) The MB86391 negates XBUSEN and resets to its normal state. Notes: The burst length is fixed to 4. After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed. Burst access extending over 1 KB is not allowed.
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3.1.1.3 External Resource Accessing
(a) Write
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS( I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' WD WD All `H ' All `H ' WA
All `H'
WA
WA
All ` H'
Fig. 3.1.1.3a: External resource access timing (Write) (1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26,17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XRDWR, ADRS27:26, 17:2, and D31:0 and asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) The MB86391 fetches the address and control signal statuses in (3) and then negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26, 17:2 to Hi-Z. (5) After setting XREADY to Hi-Z, the MB86391 asserts the appropriate XCSn(n = 5,4) and re-outputs XAS, XRDWR, and ADRS27:26, 17:2 fetched in (4) to the external resource. (6) The external resource asserts the XREADY signal and notifies that data write is complete. (7) The MB86391 negates XBUSEN and XREADY, sets BUSDIR to `H' (read direction) and resets to its normal state. Notes: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed. The external resource needs to be set to Hi-Z after setting XREADY to 'H.'
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(b) Read
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XAS( I/O) XRDWR( I/O) ADRS27:26, 17:2(I/O) XCS5,4(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' RD All `H ' All `H ' RA
All `H'
RA
RA
All ` H'
Fig. 3.1.1.3b: External resource access timing (Read) (1) The external master asserts XBREQ and requests for bus privilege. (2) Before granting bus privilege, the MB86391 sets XAS, XRDWR, ADRS27:26, 17:2 and D31:0 to Hi-Z and BUSDIR to 'L' (write direction) and then asserts XBGRNT and XBUSEN to grant bus privilege to the external master. (3) The external master outputs valid data to XRDWR and ADRS27: 26, 17:2 at the same as it asserts the XAS signal. Note that XBREQ must be asserted up to this cycle. (4) After fetching the address and control signal statuses in (3), the MB86391 negates XBGRNT. At negation of XBGRNT, the external master needs to set XAS, XRDWR and ADRS27:26, 17:2 to Hi-Z. (5) After setting XREADY to Hi-Z, the MB86391 asserts the appropriate XCSn(n = 5,4) and re-outputs XAS, XRDWR, and ADRS27:26,17:2 fetched in (4) to the external resource. (6) The external resource asserts the XREADY signal and notifies that valid data is output to D31:0. (7) The MB86391 negates XBUSEN and XREADY, sets BUSDIR to 'H' (read direction), and resets to normal state. Notes: After negating XREADY, the next request for bus privilege (asserting XBREQ) is allowed. The external resource needs to be set to Hi-Z after setting XREADY to 'H."
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3.1.2 Internal Controller Master Accessing
Shown below are diagrams of timing according to which the MB86391 internal controller accesses peripheral chips (such as the MPEG2 decoder LSI) connected to this interface.
3.1.2.1 External Resource Accessing
(a) Write
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XRDWR( I/O) XAS( I/O) ADRS27:26, 17:2(I/O) XCS5,4(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All `H ' WD WD All ` H' All ` H' WA WA All ` H'
Fig. 3.1.2.1a: External resource access timing (Write) (1) The MB86391 sets XREADY to Hi-Z and asserts XBUSEN to prepare for accessing. (2) With XCSn (n = 5,4) asserted, the controller selects an external resource and, in conjunction with XAS assertion, outputs valid data to XRDWR, ADRS27:26, 17:2 and D31:0. (3) When the external resource asserts the XREADY signal, the MB86391 negates XCSn (n = 5,4) and sets XRDWR to 'H' (read, normal state) at the same time as the selection is cancelled (4) The controller negates the XBUSEN and XREADY signals to reset to its normal state. Note: The external resource needs to be set to Hi-Z after setting XREADY to 'H.'
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(b) Read
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XRDWR( I/O) XAS( I/O) ADRS27:26, 17:2(I/O) XCS5,4(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All ` H' RD All `H ' All ` H' RA RA All ` H'
Fig. 3.1.2.1b: External resource access timing (Read) (1) The MB86391 sets BUSDIR to 'L' (read direction) and XREADY to Hi-Z and asserts XBUSEN to prepare for accessing. (2) With XCSn (n = 5,4) asserted, the MB86391 selects an external resource and, in conjunction with XAS, outputs valid data to ADRS27:26, 17:2. (3) When the external resource outputs valid data to D31: 0 and asserts the XREADY signal in the next cycle, the MB86391 reads the data, negates XCSn(n = 5,4), and cancels the selection. (4) The controller sets BUSDIR to `H' (write direction), negates the XBUSEN and XREADY signals, and resets to its normal state. Note: The external resource needs to be set to Hi-Z after setting XREADY to 'H.'
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3.1.2.2 External Boot ROM Read
BCLK(O) XBREQ(I) XBMREQ(I) XBGRNT(O) XRDWR( I/O) XAS( I/O) ADRS27:26, 17:2(I/O) XCS0(O) XREADY( I/O) D31:0( I/O) XBUSEN(O) BUSDIR(O)
All ` H' RD All ` H' All ` H' RA RA All ` H'
Fig. 3.1.2.2: External boot ROM access timing (Read) (1) With XCS0 asserted, the MB86391 selects the external boot ROM, sets BUSDIR to 'L' (read direction) and XREADY to Hi-Z, and asserts XBUSEN to prepare for accessing. (2) In conjunction with XAS, the MB86391 outputs valid data to ADRS27:26, 17:2 (let the external boot ROM output read data to the data bus after confirming XCS0). (3) After proper wait cycles, the MB86391 reads data and negates XCSO to cancel the selection. (4) The MB86391 sets BUSDIR to `H' (write direction), negates the XBUSEN and XREADY signals, and resets to its normal state. Note: The number of read wait cycles can be set in the boot program according to the ROM in use. When defaulted, accessing is done with 30 wait cycles.
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3.1.3 Interruption
3.1.3.1 Internal Controller Interrupt Input (IRQ9:8)
This is the interrupt input to the internal controller. Use this input, for example, to control (using dedicated firmware) the MB86373 (MPEG2 decoder LSI) with the internal controller. When not in use, connect the input to either OPEN or VDDE (fixed to High).
3.1.3.2 Host Interrupt Output (XEXTIRPT)
This is the interrupt output from the internal controller to the external host. The firmware dedicated to the internal controller notifies the external host of the end of command processing, for example. (For more information, see "MB86391 Control Protocol Command Specification (Parallel I/F)").
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3.1.4 Address Map
Table 3.1.4: MB86391 address map
Address
*1
Size (byte) 4K 252K 128K 128K 8M 64K 64K 64K 64K 64K 64K 64K 64K
CSn CS0 CS0 CS4 CS5 - - - - - - - - -
Description Internal boot ROM (for internal boot) External ROM (for external boot) External chip select 4 External chip select 5 External SDRAM (8Mbytes)*2 TBC controller & filter SDRAM controller DMA controller Video encoder PES converter Multiplexing controller AUDIO buffer Internal controller (internal register)
0x0000000 to 0x0000FFF 0x0001000 to 0x003FFFF 0x4000000 to 0x401FFFF 0x4020000 to 0x403FFFF 0x8000000 to 0x87FFFFF 0xC000000 to 0xC00FFFF 0xC010000 to 0xC01FFFF 0xC020000 to 0xC02FFFF 0xC100000 to 0xC10FFFF 0xC200000 to 0xC20FFFF 0xC300000 to 0xC30FFFF 0xC400000 to 0xC40FFFF 0xC800000 to 0xC80FFFF
*1: Any space with no description is reserved. *2: An area of 4 Mbytes is actually used.
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3.2
Serial Interface
The serial interface is provided for serial boot and serial API. Since this interface does not control flow with hardware, you need to control the flow with firmware such as a driver. The firmware dedicated to the internal controller uses ASCII mode.
3.2.1 Serial Interface Receive Operations
The serial interface supports the following receive data formats:
MODE ASCII Data32 FM1 0 1 FM2 MSB 0 Data section bit count (N) 7 32 Description ASCII code 0x00 to 0x7F and others 32-bit binary data
Fig. 3.2.1a-b shows serial interface receive timings.
SCLK
SDATAIN
FM 1=0
FM 2= Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Parity
Format Start Bit Stop Bit
Fig. 3.2.1a: Serial interface receive timings (ASCII mode)
SCLK
SDATAIN
FM1=1
FM2=0
Bit31
Bit30
Bit29
Bit28
Bit27
Bit0
Parity
Format Start Bit Stop Bit
Fig.3.2.1b: Serial interface receiver timing (Dara32 mode) There are 2 type transport mode (SCLK synchronization mode and start-stop synchronization mode). When using start-stop synchronization mode, pull the SDATAOUT pin down with about 3.3k. When using SCLK synchronization mode, pull the SDATAOUT pin up with about 3.3k. It is not possible to change the transport mode during working. In SCLK synchronization mode, data is taken on raising edge of SCLK. In start-stop synchronization mode, data is taken according to 9600bps with reference to the StartBit falling edge of the SDATAIN signal regardless of SCLK. Use even parity from FM1 through DataN. After the parity bit, 1 is needed as StopBit. However, if 0 is received at this point, it is recognized as a break signal and invalidates receive data.
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3.2.2 Serial Interface Send Operations
The serial interface supports the following send data formats
MODE ASCII Data32 FM1 0 1 FM2 MSB 0 Data section bit count (N) 7 32 Description ASCII code 0x00 to 0x7F and others 32-bit binary data (for others)
Fig. 3.2.2a-b shows serial interface send timings.
SCLK
SDATA OUT
FM1=0
FM 2= Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Parity
Format Start Bit Stop Bit
Fig. 3.2.2a: Serial interface send timings (ASCII mode)
SCLK
SDATA OUT
FM1=1
FM2=0
Bit31
Bit30
Bit29
Bit28
Bit27
Bit0
Parity
Format Start Bit Stop Bit
Fig. 3.2.2b: Serial interface send timings (DATA32 mode)
There are 2 type transport mode (SCLK synchronization mode and start-stop synchronization mode). When using start-stop synchronization mode, pull the SDATAOUT pin down with about 3.3k. When using SCLK synchronization mode, pull the SDATAOUT pin up with about 3.3k. It is not possible to change the transport mode during working. Use even parity from FM1 through DataN.
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3.3
SDRAM Interface for Video Encoding
The SDRAM interface for video encoding controls access to an external SDRAM that the video encoder built into this LSI uses to encode video input data. Connect either two 16Mbit (512Kx16bitx2bank configuration) SDRAMs or one 64Mbit (512Kx32bitx4bank configuration) SDRAM. Fig. 3.3 shows an example 64Mbit SDRAM connection.
64Mbit SDRAM (MB81F643242B and others)
BA0 BA1, A10:0 DQ31:0 DQM3:0 WE CAS RAS CS CKE CLK `Fixed to H' or `L'
MB86391
SDADRS11:0 SDDATA31:0 SDDQM XSDWE XSDCAS XSDRAS XSDCS SDCKE SDCLK Video encoding SDRAM interface
Note: Install the MB86391 and the SDRAM as physically close as possible. Pull up the SDCLK signal line with a resistance of 200 in the vicinity of the SDRAM. The SDCLK signal line must be in a pattern of a single stroke, from the MB86391, the sending end, through the SDRAM CLK to the point of connection to the pull-up resistance. Other signal lines do not require any particular handling such as pull-up. However, take care to avoid unnecessary routing when designing patterns. Fig. 3.3: Example video encoding SDRAM interface connection
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3.4
Video Input Interface
The video input interface is a dedicated interface between the MB86391 and an external device (such a an NTSC decoder) connected to the MB86391. Fig. 3.4 shows an example connection.
NTSC decoder (SAA7113)
VDO7:0 LCC "H" RTS0 RTS1 "H"
MB86391
DVIDEO7:0 VCLK XVSYNC XHSYNC FIELD XVALID Video input interface
Fig. 3.4: Example video input interface connection
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3.4.1 Input Formats
The video input interface is compatible with the following data input formats: (a) D1 parallel input mode Input D1 format data to the DVIDEO7:0 pin. The XVSYNC, XHSYNC, FIELD and XVALID pins are not used (keep them fixed to H.) since synchronization information is extracted from the SAV/EAV signal in the D1 data. (b) Y/C multiplex input mode Input video data multiplexed in 4:2:2 format (CbYCr in that order) to DVIDEO7:0 pin as well as sync and valid pixel signals to the XVSYNC, XHSYNC, FIELD and XVALID pins.
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3.5
Audio Input Interface
The audio input interface is a dedicated audio data interface between the MB86391 and the audio A/D converter connected to the MB86391. Fig. 3.5 shows an example connection.
MB86391
ASCLK LR_clock Bit_clock ALRCK ACLK ADATA Audio input interface
Audio A D C
Data
256fs
PLL
27MHz oscillation
MCLKI
Note:
MCLKI must be in sync with ASCLK. Fig. 3.5: Example audio input interface connection (Master mode)
MB86391
ASCLK LR_clock Bit_clock ALRCK ACLK ADATA Audio input interface
Audio A D C
Data
256fs
PLL
27MHz oscillation
MCLKI
Note:
MCLKI must be in sync with ASCLK. Fig. 3.5: Example audio input interface connection (Slave mode)
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3.5.1 Master/Slave Mode
Master (the MB86391 outputs ACLK and ALRCK) and slave (input of ACLK and ALRCK from the audio A/D converter to the MB86391) modes can be switched.
3.5.2 Input Formats
Setting each of the following parameters allows compatibility with various input formats: (1) MSB first/LSB first of data (2) Packing ALRCK with data (left/right packing)) (3) ALRCK polarity (`H'=Lch, 'L'=Rch / `L'=Lch 'H'=Rch) (4) Phase relationship between ALRCK and data (compatible with I2S interface) The phase relationship between ALRCK and ACLK is adjustable by 256 fs in master mode.
ACLK(I/O)
Lch Lch Rch Rch Rch Rch D MSB/LSB D
D D D
ALRCK(I/O)
Lch Lch D D D
D D D
D
D
D
D
D
D
D
D
ADATA(I) MSB/LSB
16bit
LSB/MSB D MSB/LSB D
16bit
LSB/MSB D MSB/LSB D D
D D D
16bit
LSB/MSB
16bit
LSB/MSB
Fig. 3.5.2: Input formats
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3.6
Bit Stream Output Port
(a) 27 MHz sync mode This mode is for storage function products. The PCR(SCR) is made by the calculated value from bit-stream and datasize.
The bit stream output port is compatible with various transfer modes described next:
BCLK(O) STREQ(I) STEN(O) STDATA(O) TSPSSYNC(O)
Valid Valid Valid Valid
Fig. 3.6a: 27 MHz sync mode timings (1) When ready to receive streams, set STREQ to 'H.' (2) When valid data exists, the MB86391 sets STEN to 'H' at STDATA to instruct data fetching. It also sets the TSPSSYNC signal simultaneously to 'H' at the sync byte "0x47" if the stream is TS, and at pack start code "0x000001BA" or at the leading byte of the program end code "0x000001B9" if the stream is PS. Notes: There is an instance during which two pieces of data are output at maximum even if STREQ is set 'L.' Limit the duration during which STREQ is set to 'L' while encoding to a few tens of clocks. The bit rate must also be maintained on the average (The MB86391 is equipped with an internal buffer to temporarily store bit streams. However, the buffer fails if bit streams are not read for a lengthy period of time.)
(b) Handshake mode This mode is for storage function products. The PCR(SCR) is made by the calculated value from bit-stream and datasize.
BCLK(O) STREQ(I) STEN(O) STDATA(O) TSPSSYNC(O)
Valid Valid
Fig. 3.6b: Handshake mode timings
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(1) When ready to receive streams, set STREQ to 'H.' (2) When valid data exists, the MB86391 changes STEN 'H''L' 'H' at STDATA. It simultaneously sets the TSPSSYNC signal to 'H' at the sync byte "0x47" if the stream is TS, and at the pack start code "0x000001BA" or at the leading byte of the program end code "0x 000001B9" if the stream is PS. Note: Limit the duration during which STREQ is set to 'L' while encoding to a few tens of clocks. The bit rate must also be maintained on the average (The MB86391 is equipped with an internal buffer to temporarily store bit streams. However, the buffer fails if bit streams are not read for a lengthy period of time.)
(c) External clock sync mode(CBR) This mode is for real time transfer function products. The PCR(SCR) is made by STCLK.
STCLK(I) STREQ(I) STEN(O) STDATA(O) TSPSSYNC(O)
Valid Valid Valid Valid
Fig. 3.6c: External clock mode (CBR) (1) Input the transfer clock to STCLK according to the bit and set STREQ to 'H.' (2) While transferring, the MB86391 outputs 'H' to STEN at all times and outputs valid data according to the external clock STCLK. It also simultaneously sets the TSPSSYNC signal to 'H' at the sync byte "0x47" if the stream is TS, and at the pack start code "0x000001BA" or at the leading byte of the program end code "0x000001B9" if the stream is PS. Note: STCLK should be input over 1/8 x system bit-rate. (EX: When the system bit-rate is 8Mbps, STCLK should be over 1MHz.) When STCLK is more high frequency than system bit-rate which is setted, stuffing is implemented.
(d) External clock sync mode (VBR) This mode is for real time transfer function products. The PCR(SCR) is made bySTCLK.
STCLK(I) STREQ(I) STEN(O) STDATA(O) TSPSSYNC(O)
Valid Valid Valid Valid
Fig. 3.6d: External clock mode (VBR)
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(1) Input the transfer clock to STCLK according to the bit and set STREQ to 'H.' (2) While transferring, the MB86391 outputs 'H' to STEN at all times and outputs valid data according to the external clock STCLK. It also simultaneously sets the TSPSSYNC signal to 'H' at the sync byte "0x47" if the stream is TS, and at the pack start code "0x000001BA" or at the leading byte of the program end code "0x000001B9" if the stream is PS. Note: Stuffing is implemented as necessary.
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3.7
Error Notification Function
The MB86391 has a built-in function to notify outside of an error when it occurs. In case of an error, it sets the XERROR pin to 'L' to output error information from the bit stream output port. When the error information is output, the STEN and TSPSSYNC pins are set to 'L' (Fig.3.7). Tables 3.7a and 3.7b list the pins and error descriptions related to occurrence of errors. Table 3.7a: Error list
Pin status STDATA 54321 - 1 0 0 - - - - Sub-error code Sub-error code Sub-error code Error description No error (normal stream output) Timeout error External illegal access error Program error
XERROR 1 0 0 0
7 - 0 0 1
6 - 0 1 0
0 -
STEN - 0 0 0
TSPSSYNC - 0 0 0
Table 3.7b: Sub- error code list
Sub- error code 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 to 1 0 0 0 0 1 1 1 1 0 to 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 Reserved 1 0 1 0 1 0 1 0 1 0 1 Boot complete Boot in progress Boot mode error Boot header keyword error Boot header checksum error Data block header keyword error Data block header checksum error Data block checksum error Reserved Description Reset status Firmware startup
Note: Being dependent on the firmware, this code is subject to change and addition.
BCLK(O) TSPSSYNC(O) STEN(O) STDATA(O) XERROR(O)
2cycle(max.) ERROR
Fig. 3.7: Error information output timings
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3.8
Boot Operations
The MB86391 starts booting operations when the internal controller starts the boot program of the internal ROM. The program required for the operation is downloaded to the SDRAM interface connected to the host/SDRAM according to the processing flow in Fig. 3.8. Each downloading procedure is described in the next and subsequent chapters.
Start boot
Initialize
Check external ROM keyword
Keyword OK? NO Check serial API
YES
External ROM download
Data exists? NO Check parallel API
YES
Serial download
Startup request? NO
YES
Immediately start SDRAM.
Fig. 3.8: Booting flow
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3.8.1 Downloading from the External ROM
This mode downloads the program from an external ROM to the SDRAM. When the boot program of the internal ROM confirms of the external ROM, start downloading from the external ROM to SDRAM via MB86391. After downloading, MB86391 starts the program on SDRAM. When the existence of an external ROM is confirmed, the program re-sets the wait count specified with "wait" in the header to download the data to be downloaded. The download data configuration is not dependent on the ROM bus width.
3.8.2 Serial Download
The internal ROM boot program of the MB86391 sets to either serial API or SDRAM direct download mode (see Chapter 3.8.3) if it confirms that there is no external ROM. Upon arrival of an interrupt from the serial interface, the internal ROM boot program of the MB86391 receives the data transferred with the serial interface and, if the header of this data is configured as shown in Table 3.8.2a, downloads it as serial API. The internal serial interface of the MB86391 supports Data32 and ASCII send and receive data formats (see Chapter 3.2). Since data can also be sent with SCLK synchronization or Asynchronization (9,600bps), four types of serial booting are available (Data32/SCLK synchronization, ASCII/SCLK synchronization, Data32/Asynchonization, and ASCII/Asynchronization).
3.8.3 Direct SDRAM Downloading
The SDRAM connected to the MB86391 host/SDRAM is assigned in the CS1 space by the internal ROM boot initialization routine. From the host interface with the parallel API, the entire SDRAM area is accessible if used with a bank register. This enables to write the program and data (including the header in Table 3.8.3) from the host/SDRAM interface to the SDRAM by directly accessing the memory. During this period, the internal ROM boot program of the MB86391 is in an infinite loop waiting for interruption. Therefore, from the host/SDRAM interface, instruct to start the program by executing parallel API interruption (by writing to the register) after direct downloading to the SDRAM is complete. The internal ROM boot program of the MB86391 verifies that the appropriate header is in from the SDRAM leading address and then jumps to the Entry Address to start executing the program.
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4 Electrical Characteristics
4.1 Maximum Ratings
Table 4.1: Maximum ratings
Item Supply voltage*1 Input voltage Output voltage Output current Operating temperature Storage temperature Symbol VDDI VDDE AVDD VI VO IO Ta TST Max. ratings -0.5 to 2.5 -0.5 to 4.0 -0.5 to 2.5 -0.5 to VDDE+0.5 (4.0) -0.5 to VDDE+0.5 (4.0) +13/-13 -20 to 85 -55 to 125 Unit V V V mA C C
*1: VDDI - Internal logic power supply, VDDE - External I/O power supply, AVDD - PLL power supply
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4.2
Recommended Operating Conditions
4.2.1 Recommended Operating Conditions
Table 4.2.1: Recommended operating conditions
Item Symbol VDDI VDDE AVDD H-level input voltage L-level input voltage 3.3V VIH Min. 1.65 3.0 1.65 2.0 Ratings Typical 1.8 3.3 1.8 - Max. 1.95 3.6 1.95 VDDE+0.3 V Unit
Supply voltage
V
3.3V
VIL Ta
-0.3 -20
- 25
0.8 85
V C
Operating temperature
4.2.2 Precautions When Connecting the Power
* Although VDDI, VDDE and AVDD can be turned on and off in any order, Fujitsu recommends
the following order: Turning on:VDDI, AVDD(internal) VDDE(external) signals Turning off:signals VDDE(external) VDDI, AVDD(internal) Do not keep VDDE (external) alone pressed (for more than a few seconds) with VDDI and AVDD (internal) disconnected.
* The following power supply sequence applies to 5V tolerant I/O
Before turning on the device, never input 5V input signals (observe the maximum ratings at all times). Otherwise, you might destroy the device.
* After turning on the power, keep the PLLTHR pin set to the L level for more than 2s. Next,
set the PLLTHR pin to the H level and then input the L level to the XRESET signal for more than 300s.
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4.3
DC Characteristics
Ratings Typical - - - - - 25 -
Measurement conditions:VDDI=1.65 to 1.95V, VDDE=3.0 to 3.6, VSS=0.0V, Ta=-20 to 85C
Item H-level output voltage*1 L-level output voltage*2 H-level output current*3 L-level output current*4 Input leakage current Pull up/down resistance Pin capacity Symbol VOH VOL IOH1 *6 IOH2 *5 IOL1 *6 IOL2 *5 IL Rp C Min. VDDE-0.2 0.0 -4.0 -8.0 4.0 8.0 - 10 - Max. VDDE 0.2 - - +5 / -5 70 16 Unit V V mA mA A k PF
*1: Condition IOH=-100A *2: Condition IOL=100A *3: Condition VOH=VDDE-0.4V *4: Condition VOL=0.4V *5: BCLK, SPSDCLK, and SDCLK signal output characteristics *6: Output characteristics of signals other than those in *5
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4.4
AC Characteristics
4.4.1 Overall Control
4.4.1.1 Clock Input
1/f MCLKI t HMCLKI t LMCLKI
MCLKI
Item MCLKI frequency MCLKI H duration MCLKI L duration
Symbol fMCLKI tHMCLKI tLMCLKI
Condition
Min. - 14 14
Standard Typical 27 - -
Max. - - -
Unit MHz ns ns
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4.4.1.2 Reset Input
(a) After turning the power on
PLLTHR
tLPLLTHR XRESET
tLRESET
Item PLLTHR L duration XRESET L duration
Symbol tLPLLTHR tLRESET
Condition
Min. 2 300
Standard Typical - -
Max. - -
Unit s s
(b) Other than after turning the power on
XRESET
tLRST
Item XRESET L duration
Symbol tLRST
Condition
Min. 500
Standard Typical -
Max. -
Unit ns
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4.4.2 Host/SDRAM Interface
4.4.2.1 Host Interface
Clock (BCLK)
1/fBCLK tHBCLK tLBCLK
BCLK
Item BCLK frequency BCLK H duration BCLK L duration
Symbol fBCLK tHBCLK tLBCLK
Condition
Min. - 13 13
Standard Typical 27 - -
Max. - - -
Unit MHz ns ns
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Input sigals
BCLK
ADRS, D, IRQ, XAS, XRDWR, XBMREQ, XBREQ, XREADY
t IADRSS, tIDS, tIRQS , t IASS, t IRWS, t BMRQS, t BRQS, tIRDYS
tIADRSH, tIDH, t IRQH, t IASH, tIRWH, tBMRQH, t BRQH, t IRDYH
Output signals
BCLK
ADRS, D, XAS, XRDWR, XCS, XBGRNT, XBUSEN, BUSDIR, XREADY, XEXTIRPT, XERROR t OADRSD, t ODD, tOASD , t ORWD, t CSD, t BGRNTD, tBED, t BDD, tORDYD , tEID, tERRD
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Item Address input setup time Address input hold time Address output delay time Data input setup time Data input hold time Data output delay time IRQ setup time IRQ hold time XBREQ setup time XBREQ hold time XBMREQ setup time XBMREQ hold time XBGRNT delay time XRDWR input setup time XRDWR input hold time XRDWR output delay time XAS input setup time XAS input hold time XAS output delay time XCS delay time XREADY input setup time XREADY input hold time XREADY output delay time XBUSEN delay time BUSDIR delay time XEXTIRPT delay time XERROR delay time
Symbol tIADRSS tIADRSH tOADRSD tIDS tIDH tODD tIRQS tIRQH tBRQS tBRQH tBMRQS tBMRQH tBGRNTD tIRWS tIRWH tORWD tIASS tIASH tOASD tCSD tIRDYS tIRDYH tORDYD tBED tBDD tEID tERRD
Condition
Min. 7 0.5 3 7.5 0 3 7 0 7 0 7 0 3 7 0 3 7 0 3 3 7 0 3 3 3 3 3
Standard Typical - - - - - - - - - - - - - - - - - - - - - - - - - - -
Max. - - 12 - - 12 - - - - - - 12 - - 12 - - 12 12 - - 12 12 12 12 12
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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4.4.2.2 SDRAM Interface Signals
Clock (SPSDCLK)
1/f SPSDCLK tHSPSDCLK tLSPSDCLK
SPSDCLK
Item SPSDCLK frequency SPSDCLK H duration SPSDCLK L duration
Symbol fSPSDCLK tHSPSDCLK tLSPSDCLK
Condition
Min. - 6.5 6.5
Standard Typical 54 - -
Max. - - -
Unit MHz ns ns
Input signals
SPSDCLK
D31:0
t RDS
t RDH
Output signals
SPSDCLK
D31:0, ADRS14:2, XSPWE, XSPCAS, XSPRAS, SPCKE tWDD, tADRSD , tSPWED, tSPCASD , tSPRASD , tSPCKED
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Item Address output delay time Read data setup time Read data hold time Data output delay time SPWE delay time SPCAS delay time SPRAS delay time SPCKE delay time
Symbol tADRSD tRDS tRDH tWDD tSPWED tSPCASD tSPRASD tSPCKED
Condition
Min. 3 7 0 3 3 3 3 3
Standard Typical - - - - - - - -
Max. 12 - - 12 12 12 12 12
Unit ns ns ns ns ns ns ns ns
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4.4.3 Serial Interface
Clock (SCLK)
1/fSCLK tHSCLK tLSCLK
SCLK
Item SCLK frequency SCLK H duration SCLK L duration
Symbol fSCLK tHSCLK tLSCLK
Condition
Min. - 200 200
Standard Typical - - -
Max. 2 - -
Unit MHz ns ns
Input signals
SCLK
SDATAIN
t SDIS
t SDIH
Output signals
SCLK
SDATAOUT
tSDOD
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Item Serial data input setup time Serial data input hold time Serial data output delay time
Symbol tSDIS tSDIH tSDOD
Condition
Min. 100 100 -
Standard Typical - - -
Max. - - 160
Unit ns ns ns
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4.4.4 SDRAM Interface for Video Encoding
Clock (SDCLK)
1/fSDCLK tHSDCLK tLSDCLK
SDCLK
Item SDCLK frequency SDCLK H duration SDCLK L duration
Symbol fSDCLK tHSDCLK tLSDCLK
Condition
Min. - 6.5 6.5
Standard Typical - - -
Max. 54 - -
Unit MHz ns ns
Input signals
SDCLK
SDDATA31:0
t RSDS
t RSDH
Output signals
SDCLK
SDDATA31:0, SDADRS11:0, SDDQM, XSDWE, XSDCAS, XSDRAS, XSDCS, SDCKE tWSDD, t SADRSD, t SDDQM, tSDWED , tSDCASD , t SDRASD, t SDCSD , t SDCKED
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Item Address output delay time Read data setup time Read data hold time Data output delay time XSDDQM delay time XSDWE delay time XSDCAS delay time XSDRAS delay time XSDCS delay time XSDCKE delay time
Symbol tSADRSD tRSDS tRSDH tWSDD tSDDQM tSDWED tSDCASD tSDRASD tSDCSD tSDCKED
Condition
Min. 3.5 5.5 0 3.5 3.5 3.5 3.5 3.5 3.5 3.5
Standard Typical - - - - - - - - - -
Max. 13 - - 13 13 13 13 13 13 13
Unit ns ns ns ns ns ns ns ns ns ns
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4.4.5 Video Input Interface
Clock (VCLK)
1/f VCLK tHVCLK t LVCLK
VCLK
Item VCLK frequency VCLK H duration VCLK L duration
Symbol fVCLK tHVCLK tLVCLK
Condition
Min. 27 11 11
Standard Typical - - -
Max. 36 - -
Unit MHz ns ns
Input signal
VCLK
XVSYNC, XHSYNC, FIELD, XVALID, DVIDEO
tVSYNCS , t HSYNCS, tFLDS, t VLDS, tDVDS Item XVSYNC setup time XVSYNC hold time XHSYNC setup time XHSYNC hold time FIELD setup time FIELD hold time XVALID setup time XVALID hold time DVIDEO setup time DVIDEO hold time Symbol tVSYNCS tVSYNCH tHSYNCS tHSYNCH tFLDS tFLDH tVLDS tVLDH tDVDS tDVDH
tVSYNCH , tHSYNCH, tFLDH, tVLDH, tDVDH Condition Standard Typical - - - - - - - - - - Unit ns ns ns ns ns ns ns ns ns ns
Min. 10 0 10 0 10 0 10 0 10 0
Max. - - - - - - - - - -
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4.4.6 Audio Input Interface
(a) In master mode System clock input (ASCLK)
tASCLK t HASCLK tLASCLK
ASCLK
Item ASCLK frequency ASCLK H duration ASCLK L duration
Symbol tASCLK tHASCLK tLASCLK
Condition
Min. - 30 30
Standard Typical
1/256fs
- -
Max. - - -
Unit ns ns ns
Note: fs: Audio sampling frequency Audio bit clock output (ACLK)
ASCLK
t ACLKD tACLKO tHACLKO tLACLKO
ACLK
Item ACLK frequency ACLK H duration ACLK L duration ACLK delay time
Symbol tACLKO tHACLKO tLACLKO tACLKD
Condition
Min. - 135 135 3
Standard Typical
1/64fs
Max. - - - 15
Unit ns ns ns ns
- - -
Note: fs: Audio sampling frequency
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Serial audio data input signals
ACLK
ADATA
t ADS
t ADH
Audio sampling clock output signals
ASCLK
ALRCK
tALRCKD t ALRCKO
Item ADATA setup time ADATA hold time ALRCK cycle time ALRCK delay time
Symbol tADS tADH tALRCKO tALRCKD
Condition
Min. 50 50 20 3
Standard Typical
Max.
Unit ns ns s ns
15
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(b) In slave mode Audio bit clock input (ACLK)
t ACLKI tHACLKI tLACLKI
ACLK
Item ACLK cycle duration ACLK H duration ACLK L duration
Symbol tACLKI tHSDCLK tLSDCLK
Condition
Min. - 135 135
Standard Typical
1/64fs
Max. - - -
Unit ns ns ns
- -
Note: fs: Audio sampling frequency
Serial audio data input signals
ACLK
ADATA
t ADS
t ADH
Audio sampling clock input signals
ACLK
ALRCK
t ALRCKH tALRCKI MB86391 Product Specification Rev. 1.1
t ALRCKS
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Item ADATA setup time ADATA hold time ALRCK cycle time ALRCK setup time ALRCK hold time
Symbol tADS tADH tALRCKI tALRCKS tALRCKH
Condition
Min. 50 50 20 50 50
Standard Typical
Max.
Unit ns ns s ns ns
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4.4.7 Bit Stream Output Port
(a) 27 MHz sync/handshake mode Input singnals
BCLK
STREQ
t BSTRQS tBSTRQH
Output signals
BCLK
STEN, STDATA, TSPSSYNC
t BSTED, tBSTDTD, t BTPSYNCD
Item STREQ setup time STREQ hold time STEN delay time STDATA delay time TSPSSYNC delay time
Symbol tBSTRQS tBSTRQH tBSTED tBSTDTD tBTPSYNCD
Condition
Min. 8 0 5 5 5
Standard Typical
Max.
Unit ns ns ns ns ns
15 15 15
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(b) Transfer clock sync mode Clock (STCLK)
tSTCLK t HSTCLK t LSTCLK
STCLK
Item STCLK cycle duration STCLK H duration STCLK L duration
Symbol tSTCLK tHSTCLK tLSTCLK
Condition
Min. 150 60 60
Standard Typical
Max.
Unit ns ns ns
Input signals
STCLK
STREQ
t STRQS
t STRQH
Output signals
STCLK
STEN, STDATA, TSPSSYNC
t STED, t STDTD, t TPSYNCD
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Item STREQ setup time STREQ hold time STEN delay time STDATA delay time TSPSSYNC delay time
Symbol tSTRQS tSTRQH tSTED tSTDTD tTPSYNCD
Condition
Min. 0 60
Standard Typical
Max.
Unit ns ns ns ns ns
103 103 103
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